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engineering specification type 20.8 qxga color tft/lcd module model name:ITQX20E document control number : oem i-920e-03 note:specification is subject to change without notice. consequently it is better to contact to international display technology before proceeding with the design of your product incorporating this module. sales support international display technology engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 1/42
i contents i contents ii record of revision 1.0 handling precautions 2.0 general description 2.1 characteristics 2.2 functional block diagram 2.2.1 interface summary 3.0 absolute maximum ratings 4.0 optical characteristics 5.0 signal interface 5.1 connectors 5.2 interface signal description 5.3 interface signal electrical characteristics 5.4 inverter connector signal description 5.5 dc/dc connector signal description 6.0 pixel format image 7.0 interface timings 7.1 timing characteristics 8.0 power consumption 9.0 power on/off sequence 10.0 color adjustment 10.1 color adjustment overview 10.2 color adjustment spacifications 10.2.1 white point adjustable chromaticity coordinates range 10.2.2 luminance degradation 10.2.3 chromaticity coordinates uniformity over the achromatic colors 10.3 input prameters details 10.3.1 input parameters setting interface (i2c) 10.3.2 data registers assignment for color adjustment 10.3.3 ca mode register 10.3.4 ragisters to set parameters for white point adjustment 10.3.5 concept figures for the adjustment 10.4 i2c specification 10.4.1 i2c feature summary 10.4.2 electrical specification 10.4.3 timing specification 10.4.4 data format specification 10.4.5 ganeral call address reset 11.0 mechanical characteristics 12.0 national test lab requirement 13.0 application note 13.1 luminance vs temperature 13.2 design recommendation 13.2.1 recommendations for cooling 13.2.2 mechanical recommendation for monitor enclosure design 13.2.3 recommendation of designing monitor which uses ITQX20E for emc compliance engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 2/42
ii record of revision to update value of shock test criteria. to correct note of minimum white luminance. to update j1/j2 connector (on x-cards). to correct the value of the following timing characteristics items. (there is no design changes.) (min. value) !" total line (max. value) "! h-front porch " h-active level " h-back porch to update reference drawings. 8 9 10 23 36,37 oem i-920e-03 march 12,2002 updated by establishment of the new company as "international display tecnology". to avoid using "inch" indication. 1,5,6 oem i-920e-02 february 22,2002 based on internal spec. ec f79103. to update handling precauitons. to update min. backlight on signal. to update interface signal electrical characteristics. to correct a typo of tolerance from + 0.6 to + 0.8 on the drawing. to update max.temperature for x-driver. 4 8 16,17 36 40 oem920e-02 november 20,2000 first edition for customer. based on internal spec. as of july 28,2000. all oem920e-01 september 1,2000 summary page document revision date engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 3/42
1.0 handling precautions ? damage to the panel or the panel electronics may result from any deviation from the recommended power on/off sequencing. the panel should not be hot plugged. refer to the power on/off sequence section in this specification. ? handle the panel with care. the lcd panel and ccfl (cold cathode fluorescent lamp)s are made of glass and may crack or break if dropped or subjected to excessive force. ? the ccfls contain a small amount of mercury so should not be disposed of to landfill. dispose of as required by local ordinances or regulations. ? the lcd module contains small amounts of material having no flammability grade. the exemption conditions of the flammability requirements (4.4.3.3, iec60950 or ul1950) should be applied. ? the panel may be damaged by the application of twisting or bending forces to the module assembly.care should be taken in the design of the monitor housing and the assembly procedure to prevent stress damage to the panel especially the lamp cable and the lamp connector.. ? use standard earthing/grounding procedures to prevent damage to the cmos lsi while handling the module. ? use earthing/grounding procedures, an ionic shower, or similar to prevent static damage while removing the protective front sheet. ? the front polarizer can be easily damaged. take care not to scratch the front surface with any hard or abrasive material. dust, finger marks, grease etc. can be removed with a soft damp cloth (a small amount of mild detergent can be used on the damp cloth). do not apply water or datergent directly to the front surface as this may cause staining or damage the electronic components. ? never use any solvent on the front polarizer or module as this may cause permanent damage. ? do not open or modify the module assembly. ? continuous operation of the panel with the same screen content may result in some image sticking. over 10 hours operation with the same content is not recommended. ? wipe off water drop immediately. long contact with water may cause discoloration or spots. ? when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth. the information contained herein may be changed without prior notice. it is therefore advisable to contact international display technology before proceeding with the design of equipment incorporating this product. ! the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by international display technology for any infringements of patents or other right of the third partied which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of international display technology or others. ! engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 4/42
2.0 general description this specification applies to the type 20.8 color tft/lcd module 'ITQX20E'. this module is designed for a lcd monitor style display unit.this module includes an inverter card for backlight. the screen format and electrical interface are intended to support the qxga (2048(h) x 1536(v)) screen. supported colors are native 16m colors(rgb 8-bit data driver). all input signals are lvds(low voltage differential signaling) interface compatible. 2.1 characteristics the following items are characteristics summary on the table under 25 degree c condition: 0 to +50 (note2 ) -20 to +60 temperature range [degree c] operating storage (shipping) lvds (5 pairs) x 4 (right x 2, left x 2) electrical interface 64 max power consumption [w] +12 +/- 5% input voltage [v] 50 typ. optical rise time/fall time [msec] 300 : 1 typ. contrast ratio 235 typ. (note1) white luminance [cd/m 2 ] 16m (rgb 8-bit data) support color normally black display mode 457.0(w) x 350.0(h) x 45.0(d) typ.(w/inverter) physical size [mm] 2,300 typ. weight [grams] r,g,b vertical stripe pixel arrangement 0.207(per one triad) x 0.207 pixel pitch [mm] 423.9(h) x 318.0(v) active area [mm] 2048(x3) x 1536 pixels h x v 528 screen diagonal [mm] specifications characteristics items note1 : in case when color adjustment function is not used. note2 : max. operating temperature 50 degree c in the spec means the temperature measured for the point of the front surface of the lcd glass cell. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 5/42
2.2 functional block diagram the following diagram shows the functional block of this type 20.8 color tft/lcd module. type 20.8 tft-lcd module functional block diagram tft/lcd array/cell 2048x1536 y-card backlight unit + inverter card tft-lcd module +12v/1.5a +12v/4.0a lvds signals (odd/even) ifx-card asic asic fi-twe31p j1 j2 left(master) right(slave) front view dc/dc card il-z-8pl-smty-j601 s12b-ph-sm3-tb i2c signals ifx-card *1 *2 *3 *2 : 15.6v 400ma 3.3v 350ma *1 : 15.6v 400ma 3.3v 350ma 27.0v 10ma (for y-card) -8.5v 100ma (for y-card) 3.3v 5ma (for y-card) *3 27.0v 10ma -8.5v 100ma 3.3v 5ma or fi-twa31p engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 6/42
2.2.1 interface summary ! 4 sets of lvds interface for video input ( 65mhz typ per set, r/g/b 24 bits total, 8bits per color ) ! voltage control or i2c interface ( 3.3v ) control for brightness and contrast control ! power ( +12v ) for logic ! power ( +12v ) for backlight ITQX20E tft-lcd module does not have any frame buffer. image expansion ( scaling ) should be managed by a device driving this module and the device should supply constant timings with the frame locked to this module . ITQX20E has 4 sets of lvds interface and they are bundled to two channels. the screen is divided into two half-size screens ( left and right ) and each channel controls one of the half-size screens. each lvds interface is named as : ! lvds-le ( left screen, even dot ) : left channel ! lvds-lo ( left screen, odd dot ) : left channel ! lvds-re ( right screen, even dot ) : right channel ! lvds-ro ( right screen, odd dot ) : right channel the left channel consists of lvds-le and lvds-lo and the right channel consists of lvds-re and lvds-ro. each channel has the following signals. ! 4 pairs of video and timing signals for even dots ( 8 bits per color ) ! 4 pairs of video signals for odd dots ( 8 bits per color ) ! 1 pair of dot clock for even dots ! 1 pair of dot clock for odd dots engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 7/42
3.0 absolute maximum ratings absolute maximum ratings of the module is as follows : (note 2) half sine wave g ms 50 11 shock (note 2) g hz 1.5 10-200 vibration (note 1) %rh 95 5 hst storage humidity (note 1) deg.c +60 -20 tst storage temperature (note 1) %rh 80 8 hop operating humidity (note 1) deg.c +50 0 top operating temperature v +5.3 -1.0 blon backlight on signal v +5.3 -0.3 vdim brightness control v +13.2 -0.3 vbl backlight voltage v +13.2 -0.3 vin logic/lcd drive voltage conditions unit max min s y mbol item note 1 : maximum wet-bulb should be 39 degree c and no condensation. max. operating temperature 50 degree c in the spec means the temperature measured for the point of the front surface of the lcd glass cell. note 2 : vibration specification - sign vibration:10-200-10hz, 1.5g, 30 min, x, y, z axis, each one time. shock specification - half sine wave:50g 11msec. -x+/-, -y+/-, -z+/- (total 6 directions), each one time shock. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 8/42
4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 degree c condition: 20 max 10 vdim-in = 3.0v minimum white luminance (%) min 200 235 vdim-in = 0v (*1) maximum white luminance (cd/m 2 ) - 0.309 white y - 0.294 white x - 0.085 blue y - 0.146 blue x - 0.611 green y - 0.292 green x (cie) - 0.340 red y chromaticity - 0.638 red x color - 25 falling (ms) - 25 rising response time - 300 contrast ratio - - 85 85 vertical (upper) k ! 10 (lower) k:contrast ratio - - 85 85 horizontal (right) k ! 10 (left) viewing angle (degrees) note typ. specification conditions item (*1) measure center of the screen. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 9/42
5.0 signal interface 5.1 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. j1/j2 connector (on x-cards) j1/j2 connector fi-w31s, fi-we31m (*1) , fi-we31mv (*1) fi-w31mv-a (*1) mating connector fi-twe31p-vf(metal shell) or fi-twa31p-vf(plastic shell) type / part number jae manufacturer signal connector connector name / designation important notice: for the j1/j2 connector and there mating connector, following combination is mandatory requirement. fi-w31s fi-w31mv-a (*1) fi-twa31p-vf(plastic shell) fi-w31s fi-we31mv (*1) fi-we31m (*1) fi-twe31p-vf(metal shell) mating connector (fpc side) j1/j2 connector note : for pin assignment, please refer to '5.1.2 lcd drive connector description'. (*1) if you use the fpc type plug, please connect the fpc gnd plane to the gnd pins instead of connecting to the shell frame ground. because the connectors on the pcb side are going to be changed to plastic mold type(fi-twa31p-vf) those do not have the metallic shell. inverter connector (cn-1 on inverter card) phr-12 mating connector s12b-ph-sm3-tb type / part number jst manufacturer signal connector connector name / designation dc/dc connector type (j601 on dc/dc card) il-z-8s-s125c3 mating connector il-z-8pl-smty type / part number jae manufacturer signal connector connector name / designation engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 10/42
5.2 interface signal description the module uses a pair of lvds receiver macro which is equivalent to thc63lvdf84a/r84a(thine electronics, inc.). lvds is a differential signal transfer technology for lcd interface and high speed data transfer device. transmitter shall be thc63lvdf83a/m83a(thine electronics, inc.) or equivalent. j1 (master) : left side (front view) signal description (j1) positive lvds differential data input (even data) rxein1+ 27 negative lvds differential data input (even data,h-sync,v-sync,dsptmg) rxein2- 26 positive lvds differential data input (even data,h-sync,v-sync,dsptmg) rxein2+ 25 negative lvds differential clock input (even clock) rxeclkin- 24 positive lvds differential clock input (even clock) rxeclkin+ 23 negative lvds differential data input (even data) rxein3- 22 positive lvds differential data input (even data) rxein3+ 21 negative lvds differential data input (odd data) rxoin0- 20 positive lvds differential data input (odd data) rxoin0+ 19 negative lvds differential data input (odd data) rxoin1- 18 positive lvds differential data input (odd data) rxoin1+ 17 negative lvds differential data input (odd data) rxoin2- 16 positive lvds differential data input (odd data) rxoin2+ 15 negative lvds differential clock input (odd clock) rxoclkin- 14 positive lvds differential clock input (odd clock) rxoclkin+ 13 negative lvds differential data input (odd data) rxoin3- 12 positive lvds differential data input (odd data) rxoin3+ 11 lvds gnd lgnd 10 digital ground dgnd 9 i2c clock (3.3v typ) sclk 8 i2c data for color adjustment/contrast/brightness (3.3v typ) sdata 7 digital ground dgnd 6 (reserved) 5 (reserved) 4 (reserved) 3 (reserved) 2 this pin must be kept 'open'. (reserved) 1 description signal name pin # engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 11/42
ground for lvds clock/data signals lvdsgnd 31 negative lvds differential data input (even data) rxein0- 30 positive lvds differential data input (even data) rxein0+ 29 negative lvds differential data input (even data) rxein1- 28 note: i2c address for brightness and contrast is '0101101'b. dac for them is dallas ds1803 or equivalent. its port-0 is for contrast and the port-1 is for brightness. reserved address of i2c is from '0010000'b to '0011111'b, and from '0110000'b to '0111111'b for color adjustment function. j2 (slave) : right side (front view) signal description (j2) positive lvds differential data input (even data) rxein3+ 21 negative lvds differential data input (odd data) rxoin0- 20 positive lvds differential data input (odd data) rxoin0+ 19 negative lvds differential data input (odd data) rxoin1- 18 positive lvds differential data input (odd data) rxoin1+ 17 negative lvds differential data input (odd data) rxoin2- 16 positive lvds differential data input (odd data) rxoin2+ 15 negative lvds differential clock input (odd clock) rxoclkin- 14 positive lvds differential clock input (odd clock) rxoclkin+ 13 negative lvds differential data input (odd data) rxoin3- 12 positive lvds differential data input (odd data) rxoin3+ 11 lvds gnd lgnd 10 digital ground dgnd 9 (reserved) 8 (reserved) 7 digital ground dgnd 6 contrast control voltage output generated by i2c command vcont-out 5 contrast control voltage (0-1.6v, 1.0vtyp for gamma2.2, 0v:brighter side) vcont-in 4 brightness dimming control voltage output generated by i2c command vdim-out 3 brightness dimming control voltage (0-3v, 0v:maxbrightness) vdim-in 2 backlight on/off signal(hi:backlight on, low:backlight off) blon 1 description signal name pin # engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 12/42
ground for lvds clock/data signals lvdsgnd 31 negative lvds differential data input (even data) rxein0- 30 positive lvds differential data input (even data) rxein0+ 29 negative lvds differential data input (even data) rxein1- 28 positive lvds differential data input (even data) rxein1+ 27 negative lvds differential data input (even data,h-sync,v-sync,dsptmg) rxein2- 26 positive lvds differential data input (even data,h-sync,v-sync,dsptmg) rxein2+ 25 negative lvds differential clock input (even clock) rxeclkin- 24 positive lvds differential clock input (even clock) rxeclkin+ 23 negative lvds differential data input (even data) rxein3- 22 note: to use i2c digital control for contrast/brightness, connect vcont-out to vcont-in, vdim-out to vdim-in. to use analogue voltage control, set vcont-out and vdim-out open, then supply appropriate analogue voltage to vcont-in and vdim-in. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 13/42
the following is lvds signal description; the signal is synchronized to dtclk. horizontal sync h-sync the signal is synchronized to dtclk. vertical sync v-sync when the signal is high, the pixel data shall be valid to be displayed. the signal is synchronized to dtclk. display timing dsptmg the typical frequency is 65 mhz. the signal is used to strobe the pixel data and dsptmg signals. all pixel data shall be valid at the falling edge when the dsptmg signal is high. data clock dtclk description signal name note : output signals from any system shall be low or hi-z state when vdd is off. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 14/42
the following is lvds data order; 1 cycle 1 cycle rxein0+ rxoin0+ rxein2+ rxoin2+ rxein1+ rxoin1+ rxein3+ rxoin3+ er3 or3 eb5 ob5 eg4 og4 er1 or1 er2 or2 eb4 ob4 eg3 og3 er0 or0 eg2 og2 dsp na eb3 ob3 na na er7 or7 v-s na eb2 ob2 eb1 ob1 er6 or6 h-s na eg7 og7 eb0 ob0 er5 or5 eb7 ob7 eg6 og6 eg1 og1 er4 or4 eb6 ob6 eg5 og5 eg0 og0 er3 or3 eb5 ob5 eg4 og4 er1 or1 er2 or2 eb4 ob4 eg3 og3 er0 or0 eg2 og2 dsp na eb3 ob3 na na rxein0- rxoin0- rxeclkin+ rxoclkin+ rxeclkin- rxoclkin- rxein2- rxoin2- rxein1- rxoin1- rxein3- rxoin3- note: r/g/b 7: msb , r/g/b 0: lsb, dsp = dsptmg, v-s = v-sync, h-s = h-sync 'na' : both high and low data are ignored. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 15/42
5.3 interface signal electrical characteristics each signal characteristics are as follows; electrical characteristics mv -100 differential input high voltage (vcm=+1.2v) vtl mv 100 differential input high voltage (vcm=+1.2v) vth unit max min condition parameter note : it is recommended to refer to the specifications of thc63lvdf84a/r84a(thine electronics, inc.) for the detail. lvds timing engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 16/42
lvds macro ac characteristics. [ns] trxc/7 trxsc data sample cycle [ns] trxc/14 trxs data sample time [ps] 600 trxsh sample data hold time (trxc=typ.) [ps] 600 trxss sample data setup time (trxc=typ.) [ns] trxc/7 trxd lvds data cycle [ns] 16.66 15.38 15.15 trxc lvds clock cycle unit max typ min symbol parameter inverter input signal electrical characteristics ma 1.0 - -1.0 current 0v:brightness max 3v:brightness min v 3.0 - 0.0 input voltage range vdim-in ma 1.0 - -1.0 current (*1) v 1.6 1.0 0.2 input voltage range vcont-in ma 1.0 - -1.0 current v 0.8 0.0 -0.1 low voltage v 5.25 3.3 2.0 high voltage blon note unit max typ min description name note 1: 0.2v : to pull the gamma curve toward darker side (ex. gamma 3.0) when x'00' is written by i2c, vcont-out voltage is about 0.2v 1.0v : gamma 2.2 when x'50' is written by i2c, vcont-out voltage is about 1.0v 1.6v : to pull the gamma curve toward brighter side (ex. gamma 1.5) when x'd0' is written by i2c, vcont-out voltage is about 1.6v under the condition of color adjust function is disabled. those numbers are approximate values. note 2 : i2c address for brightness and contrast is '0101101'b and the port-0 is for contrast and port-1 is for brightness. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 17/42
5.4 inverter connector signal description inverter connector signal description (reserved) 12 (reserved) 11 ground for vbl line rtn 6-10 +12.0v power source for backlight vbl 1-5 description signal name pin # inverter input signal electrical characteristics v 12.6 12 11.4 b/l unit drive voltage vbl note unit max typ min description name 5.5 dc/dc connector singal description dc/dc connector signal description +12.0v power supply for lcd driver cards (except inverter and backlight) vin 5-8 ground for vin line rtn 1-4 description signal name pin # dc/dc input signal electrical characteristics v 12.6 12 11.4 logic/lcd drive voltage vin note unit max typ min description name engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 18/42
the following chart is the vdim vs dimming range for your reference. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 19/42
6.0 pixel format image screen format 2047 2046 10241025 1023 1022 012 0 1 1534 1535 left screen right screen lvds-le lvds-re lvds-lo lvds-ro engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 20/42
following figure shows the relationship between the input signals and the lcd pixel format image. each sub-pixel data(r,g,b) of an even and the right adjacent odd pixel unit are sampled at the same time. pixel color arrangement even odd even odd 0 1 2047 0th line 1535th line 2046 r g b r g b r g b r g b r g b r g b r g b r g b engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 21/42
7.0 interface timings following is the video timing diagrams per channel ( a half screen refresh ) to be converted to/from the lvds interface signals. 7.1 timing characteristics even for lvds-le or lvds-re odd for lvds-lo or lvds-ro. interface timing definition tv th tvb tvf tva tha thb thf tck 01 m-1 0 1 2 3 n-2 n-1 thd vsync, hsync and display timing video signal, hsync and dot clock v-sync h-sync dsptmg dsptmg video(even) video(odd) dot clock h-sync engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 22/42
timing characteristics pixels - 1024 - n display pixels dsptmg tck - 512 - thd display clocks dsptmg tck 188 160 128 thf+tha+thb h-blank h-sync tck 172 80 8 thb h-back porch h-sync tck 172 68 8 tha h-active level h-sync tck 172 12 8 thf h-front porch h-sync tck 700 672 640 th cycle h-sync us 10.77 *1 10.34 th h-scan rate h-sync khz 96.72 96.72 92.86 1/th h-scan rate h-sync lines - 1536 - m display lines dsptmg lines 92 76 11 tvf+tva+tvb v-blank v-sync lines 64 58 7 tvb v-back porch v-sync lines 14 12 2 tva v-active level v-sync lines 14 6 2 tvf v-front porch v-sync lines 1628 1612 1547 tv total line v-sync ms 16.67 tv frame period v-sync hz 60 1/tv refresh rate v-sync ns 16.66 15.38 15.15 tck dot clock period dtclk mhz 66 65 60 fdck dot clock freq. dtclk unit max. typ. min. symbol item signal note: typical value is based on vesa standard ( xga 60hz ). h/v-sync polarity can be both positive and negative. dsptmg should be active high. v-sync should not be changed at h-sync leading edge ( +/- 6 tck ). even dot clock and odd dot clock in each channel should have completely the same clock source. the skew should be within +/- 2ns. dot clocks of the left and right channels should have completely the same clock source. but the skew between those clocks does not need to be cared. the skews of all the other signals ( h-sync, v-sync, dsptmg and video data ) should be synchronized between left and right channels and should be within +/- 4 dot clocks, respectively. *1 for this value, the smaller, the better. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 23/42
8.0 power consumption input power specifications are as follows; brightness=max w 48 44 backlight power consumption pbl v 12.6 12 11.4 backlight power voltage vbl mvp-p 100 allowable logic/lcd drive ripple noise vin ns mvp-p 100 allowable logic/lcd drive ripple voltage vin rp vin=12v all white pattern w 16 14.4 vin power pin vin=12v a 1.4 1.2 vin current iin v 12.6 12 11.4 logic/lcd drive voltage vin condition units max typ min parameter symbol engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 24/42
9.0 power on/off sequence vin power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vin is off. vin/vbl/signals power on/off sequence requirements 90% 90% 10% 10% 10% 10% 90% 90% 30ms max. and 1ms min. 30ms max. and 1ms min. 30ms min. 0 min. 0 v 0 v 0 v vin vbl signals 10% 10% 5ms min. 0 min. 0 v blon 10% 10% 10% 10% 10ms min. 100ms min. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 25/42
10.0 color adjustment 10.1 color adjustment overview the color adjustment supported for ITQX20E is a white point adjustment function based on approximations at multiple gray scale levels of achromatic colors. the white point adjustment is a technique for the user to be able to change the "white" (the brightest white at least, and even all the other achromatic colors such as various grays if possible) to a more appropriate color tone, such as bluish white or yellowish one, according to the environmental lighting condition or user's preferences. to achieve this adjustment, data conversion circuit is implemented in asic on ifx-card and is controlled by i2c registers. the following figures show the overview of this technology. color adjustment overview engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 26/42
the major features of the adjustment are as follows. - the adjustable range of the chromaticity coordinates in terms of the color temperature is from 5400k through 9300k. - keep any achromatic color at lower or medium gray scale levels close to the target coordinates of the adjustment, which enables to correct the blue shift. - support 2 types of conversion, one is a conventional way of conversion called type-a, the other is so-called a pure color luminance saving method called type-b in which the luminance of pure red, green, blue, yellow, magenta, and cyan are kept to the original level, not being affected by the adjustment. totally 5 achromatic colors are available to use as the approximation points, those are 1. l255 gray : (r,g,b) = (255,255,255) ( max gray = white ) 2. l0 gray : (r,g,b) = (0,0,0) (min gray = black ) 3. l127 gray : (r,g,b) = (127,127,127) ( 1/2 gray ) 4. l63 gray : (r,g,b) = (63,63,63 ) ( 1/4 gray ) 5. l191 gray : (r,g,b) = (191,191,191 ) ( 3/4 gray ) at the l255 gray, we can just decrease (-) the gray level of r,g, or b, on the other hand at the l0 gray we can just increase (+) the gray level of r,g, or b. for the other 3 approximation points, we can both decrease and increase the gray level of r,g, or b. user can choose any number of point from zero to five to set the adjusting value(s). that is, if chromaticity coordinates of each achromatic color on the achromatic line from l255 to l0 don't vary so much, the adjustment at only he l255 point may be enough. (1 point approximation) however, if they tend to vary a lot, we need to adjust at more points up to five. (5 points approximation) also in order to compensate the reduction of the gray scale level resolution for each color due to the adjustment of this method, the dither method is applied. 10.2 color adjustment specifications 10.2.1 white point adjustable chromaticity coordinates range any coordinates on the blackbody locus from maximum to minimum adjustable color temperature. max adjustable temperature ............ 9300k min adjustable temperature ............ 5400k 10.2.2 luminance degradation assured minimum luminance by adjusted coordinates (% against full luminance) in case of 9300k on the blackbody locus ...... 85% in case of 5400k on the blackbody locus ...... 80% 10.2.3 chromaticity coordinates uniformity over the achromatic colors assured maximum rms (root mean square) value over all the 256 achromatic colors, of the chromaticity coordinates distance data from l255 coordinates is 0.02. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 27/42
10.3 input parameters details 10.3.1 input parameters setting interface ( i2c ) ITQX20E has an i2c interface for setting parameters for the color adjustment. its voltage level is 3.3v, and the maximum frequency is 100 khz. all the setting parameters should be written at every por. otherwise the default parameters (all adjustments are disabled) are used. i2c access addresses for color adjustment are from '0010 000'b to '0011 111'b for the left ( master ) asic and from '0110 000'b to '0111 111'b for the right ( slave ) asic. 16 registers are required for each asic and normally the contents of the registers of the left and right asics are the same. and 'general call address reset' whose address is '0000 000'b is also supported. other than the addresses related to color adjustment, address '0101 101'b is supported for brightness and contrast control. for more the detailed electrical / functional specification of i2c, please refer to 10.4.4 i2c specification. 10.3.2 data registers assignment for color adjustment all the data registers are cleared at por ( set to 0 ) except for bit 4 of the ca mode register and bit 7 of the l255-r/g/b register. the set values at por make all the adjustments disable. note: b = 0 in access address is for the left(master) asic, and b = 1 for right(slave) asic. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 28/42
data registers for c/a 10.3.3 ca mode register color adjust enable : 1 bit 'h' ..... enable color adjustment function 'l' ..... disable adjustment function ( set all the other values to 0 ), but all the written data are kept. dither enable : 1 bit 'h' ..... enable extension of color resolution ( recommended ) 'l' ..... disable black as black level : 1 bit 'h' ..... l0 gray point is set to ( 0,0,0 ), even if l0-r/g/b are set. 'l' ..... l0 gray point is almost the same with l0-r/g/b setting. conversion type : 1 bit 'h' ..... conversion type-a selected 'l' ..... conversion type-b selected cadje : 1 bit ( read only ) normally 'h' . when this bit is low, color adjustment function is disabled by pcb assemble. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 29/42
10.3.4 registers to set parameters for white point adjustment [[ basic set values for 2 point approximation ]] l255-r : 7 bit unsigned (0 through 127) red decrement value at the l255 gray l255-g : 7 bit unsigned (0 through 127) green decrement value at the l255 gray l255-b : 7 bit unsigned (0 through 127) blue decrement value at the l255 gray l0-r : 5 bit unsigned (0 through 31) red increment value at the l0 gray l0-g : 5 bit unsigned (0 through 31) green increment value at the l0 gray l0-b : 5 bit unsigned (0 through 31) blue increment value at the l0 gray [[ fine adjustment set values for 3 point approximation ]] l127-r : 1 bit sign bit & 5 bit unsigned (absolute) (-31 through +31) red fine adjusting value at the l127 gray l127-g : 1 bit sign bit & 5 bit unsigned (absolute) (-31 through +31) green fine adjusting value at the l127 gray l127-b : 1 bit sign bit & 5 bit unsigned (absolute) (-31 through +31) blue fine adjusting value at the l127 gray [[ sub-fine adjustment set values for 5 point approximation ]] l63-r : 1 bit sign bit & 4 bit unsigned (absolute) (-15 through +15) red fine adjusting value at the l63 gray l63-g : 1 bit sign bit & 4 bit unsigned (absolute) (-15 through +15) green fine adjusting value at the l63 gray l63-b : 1 bit sign bit & 4 bit unsigned (absolute) (-15 through +15) blue fine adjusting value at the l63 gray l191-r : 1 bit sign bit & 4 bit unsigned (absolute) (-15 through +15) red fine adjusting value at the l191 gray l191-g : 1 bit sign bit & 4 bit unsigned (absolute) (-15 through +15) green fine adjusting value at the l191 gray l191-b : 1 bit sign bit & 4 bit unsigned (absolute) (-15 through +15) blue fine adjusting value at the l191 gray [note] sign bit : 'l' ...... positive [ex.] -1 is expressed as '10001'b 'h' ...... negative engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 30/42
10.3.5 concept figures for the adjustment in case of conversion type-a, each color is adjusted independently according to each parameter for 5 points in the registers. a figure below is an example for the red adjustment. where l127-r is (+), l63-r is (+), and l191-r is (-). dotted line indicates the calculation result caused by the parameter set at each point. the video data are adjusted by the sum of all those calculated values. conversion type-a in case of conversion type-b, each color is adjusted by considering the effect of other colors, according to each parameter of 5 points. a figure below is an example for the red adjustment . in order to make it easier to understand, the color dimension is reduced from 3 ( r,g,b ) to 2 ( r,g ). as shown in the figure, the calculation for each point for the red adjustment is effected by both red and green values. where l127-r is (+), l63-r is (+), and l191-r is (-). dotted line indicates the calculation result caused by the parameter set at each point. the video data are adjusted by the sum of all those calculated values. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 31/42
conversion type-b 10.4 i2c specification following descriptions show the i2c specifications of the control asics equipped in the lcd module which has a color adjustment feature. as for the i2c specification of dac for brightness and contrast, please refer to its own specifications ( dac : dallas ds1803 ). 2 signals ( sclk and sdata ) in the lcd module interface are commonly used for the control of both the color adjustment and the dac. the address for color adjustment is from '0010000'b to '0011111'b and from '0110000'b to '0111111'b. the address for dac is '0101101'b. its port-0 is for contrast and its port-1 is for brightness. 10.4.1 i2c feature summary - standard mode ( 100khz max ) support - 3.3v interface - slave mode operation only - reading and writing, single or sequential access protocols for color adjustment registers - register clear by general call address reset for color adjustment registers engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 32/42
10.4.2 electrical specification 2 signals ( sclk and sdata ) are equipped at the lcd module interface. sclk is the clock input as scl and sdata is the data input/output as sda. these signals should be driven by open-drain or open-collector without any pull-up resister. both signals are pulled up by 5.1k ohm resisters to 3.3v typ respectively in the lcd module. electrical specification of c/a pf 35 - ci input capacitance ua 30 -30 ioh output high impedance leakage current(*3) v 0.5 - vol output low voltage ua 30 -30 ii input leakage current @ vil-min or vih-max (*3) v - 0.4 vhys input hysteresis voltage v 3.6 2.3 vih input high voltage (*2) v 0.5 -0.5 vil input low voltage (*1) unit max min symbol note : *1 : vil (typ) = 0.9v *2 : vih (typ) = 1.8v *3 : without pull up resisters ( 5.1k ohm ) 10.4.3 timing specification in the following figure and table, slave is the control asics in the lcd module and master is the controller to drive the lcd module. "s" is the start condition and "p" is the stop condition. i2c bus timing engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 33/42
timing specification of c/a ns 50 - tsp spike suppression us - 4.0 tsu:sto setup time of stop ns 300 - tf fall time vil-max <-- vih-min ns 1000 - tr rise time vil-max --> vih-min ns 900 300 tch:dat data change from scl falling edge ( to master ) ns - 250 tsu:dat data setup time for slave us - 0 thd:dat data hold time for slave us - 4.0 thigh high time of scl us - 4.7 tlow low time of scl us - 4.0 thd:sta hold time of start us - 4.7 tsu:sta setup time of start us - 4.7 tbuf bus free time from stop to start khz 100 0 fscl frequency of scl unit max min symbol 10.4.4 data format specification both writing( master to slave ) and reading( slave to master ) data transfer formats are supported. in the following figures, "m" is master and "s" is slave. if "optional n bytes" in the figure does not exist in the data flow, the access mode becomes single access mode ( read/written data are just 1 byte ). on the other hand, if "optional n bytes" exists in the data flow, it becomes sequential access mode ( data more than 1 byte are read/written continuously ). in case of sequential access mode, each address of the following data increase by 1 automatically, and the next address of '0b11 111'b becomes '0b10 000'b ( 'b' is 0 for left and 1 for right ). engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 34/42
data format (writing) data format (reading) 10.4.5 general call address reset only when the address is '0000 000'b and the write data is '0000 0110'b, the contents of all the registers (the addresses are '0b1x xxx'b ( 'b' is 0 for left and 1 for right ) ) in both left (master) and right (slave) asics are reset except for bit 4 of ca mode and bit 7 of l255-r/g/b. this means all the functions of color adjsutment are disabled. the address '0000 000'b is a write only register. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 35/42
11.0 mechanical characteristics engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 36/42
engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 37/42
12.0 national test lab requirement the display module is authorized to apply the ul recognized mark. conditions of acceptability ! this component has been judged on the basis of the required spacings in the standard for safety of information technology equipment, including electrical business equipment, can/csa c22.2 no.950-95 *ul 1950, third edition, including revisions through revision date march 1,1998, which are based on the fourth amendment to iec 950, second edition, which would cover the component itself if submitted for listing. ! the inverter output circuit supplied with this model is a limited current circuit. ! the units are intended to be supplied by selv. ! the terminals and connectors are suitable for factory wiring only. ! the terminals and connectors have not been evaluated for field wiring. ! a suitable electrical and fire enclosure shall be provided. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 38/42
13.0 application note this section describes some outstanding characteristics of ITQX20E module and also describes some design recommendations. 13.1 luminance vs temperature the following chart shows the initial luminace transition coming along with the module temperature. 13.2 design recommendation this chapter describes the recommendation when monitor frame is designed. 13.2.1 recommendations for cooling the ITQX20E is a high luminance and high resolution panel and produces some heat. inadequate cooling can result in damage to the module or the monitor unit. cooling fans are strongly recommended to ensure correct temperature operation. because of the large panel size the use of 2 fans is recommended. the recommended position of the fans is to supplement the normal convective flow. the optimum configuration would be to input cool air at the base of the panel and exhaust hot air at the top. the exact size, position, and flow rates are a function of the monitor enclosure design. please refere to the maximum operating temperatures of the various components to verify the design. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 39/42 ITQX20E temperature characteristics (luminance)
*** reference *** see the rear side of module below; - absolutely necessary points are next two components. (6) x-driver (will get very hot.) and (1) choke coil - backlight inverter (2) transformer - dc/dc card (3) choke coil - pcb-x (4), (5) gate array the table below shows the maximum component temperature spec. 60 polarizer(cell) 105 choke coil(dc/dc) 100 transformer(inverter) 105 choke coil(inverter) 85 x-driver 100 gate array max. temperature spec. (degree c) component engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 40/42
13.2.2 mechanical recommendation for monitor enclosure design. this tft module uses ips technology to enhance viewing angle, this technology is weak against twisting and bending forces. these forces cause bad fos quality, such a un uniformity. in order to keep original fos quality, please following instruction at manufacturing and designing. 1. after installation of the tft module into an enclosure, do not twist nor bent the tft module even momentary. 2. at designing the enclosure, it should be taken into below consideration. otherwise the tft module occur uniformity problem. 2-1. material of chassis or bracket to mounting tft module should be hard material, stainless or secc or spcc. material thickness should be exceeded 1mm. 2-2. no bending/ twisting forces are applied to the tft module from out side. 2-3. no pushing force for emi grounding using metal fingers or gasket tft metal bezel, to push glass surface by tft metal bezel opening edge, is applied to tft module metal bezel wall. 2-4. at designing system front plastic bezel, do not touch and push glass surface to avoid un uniformity. 13.2.3 recommendation of designing monitor which uses ITQX20E for emc compliance a. chassis and frame ground of monitor 1. lcd module should be covered by metal chasis over all except front side. the chasis of the monitor's interface card should be designed as separate parts with the chasis of the lcd module. holes on the partition wall between the two chasis shold be as small as possible to pass through the cables. the two chassis should be contacted each other with low impedance. 2. monitor's chasis(equal chasis of lcd module)should have the contact with the frame ground of voltage source(power fg) with low impedance. 3. the chasis of lcd module should have the contact with the surrounding of front bezel by finger or something at intervals of less than 1 inch. 4. the ground of the monitor's interface card should be contacted with its chasis with low impedance. 5. the holes for thermal radiation, on chasis of lcd module or monitor's interface card, should be less than 1 inch in diameter, at intervals of less than 1 inch. we recommend the holes are about 5mm in diameter, at intervals of about 10mm to 15mm. engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 41/42
b. lvds cabel(assumption as wire type, not fpc or ffc) 1. signal pairs of the differential signals should be twisted each other with more than a turn per a centimeter. 2. the ground line would wind around the set of lvds cables(1 channel). 3. the set of lvds cables would be covered by shield mesh. to make the shield mesh contacted with the signal ground, it is possible to strip the cover of ground line wound around lvds signals. 4. ferrite core would be added to lvds cables at the point near signal source. we recommend the above works at that priority(1. is the highest). c. a ferrite core would be added to the power cable which supply +12volt to lcd module. ****** end of page ****** engineering specification (c) copyright international display technology 2002 all rights reserved. march 12,2002 oem i-920e-03 42/42

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